1. Field of the Invention
The present invention relates to a semiconductor fabrication process and more particularly to a process for fabricating semiconductors, such as high electron mobility transistor (HEMT) and heterojunction bipolar transistor (HBT) semiconductors, which eliminates damage to a device during lift-off of undesired metal.
2. Description of the Drawings
High electron mobility transistors (HEMTs) are well known in the art. Examples of such HEMTs are disclosed in U.S. Pat. Nos. 6,232,624; 6,177,685; 6,100,542; 6,049,097; 6,028,328 and 5,976,920 and commonly owned U.S. Pat. Nos. 5,668,387 and 5,528,769. HEMTs are also extensively covered in the literature: xe2x80x9cTemperature-Dependent Small Signal and Noise Parameter Measurements and Modeling on InP HEMTs,xe2x80x9d Murti et al., IEEE Transactions on Microwave Theory and Techniques, Volume 48, No. 12, December 2000, pp. 2579-2587; xe2x80x9cPseudomorphic InP HEMT""s With Dry Etched Source Vias Having 190-mW Output Power and 40% PAE at V-Band,xe2x80x9d by Grundbacher et al., IEEE Electron Device Letters, Volume 20, No. 10, October 1999, pp. 517-519; and xe2x80x9cInP HEMT""s With 39% PAE and 162-mW Output Power at V-Band,xe2x80x9d Grundbacher et al., IEEE Microwave and Guided Wave Letters, Volume 9, No. 6, June 1999.
Such HEMTs are used in various low-noise and power microwave applications where relatively high-device output power, power added efficiency and noise performance are critical. Such HEMTs have been known to be used in Q, V and W-Band microwave applications in commercial and military radar systems and communication systems.
Such HEMTs are known to be integrated into monolithic microwave integrated circuits (MMICS) for use in various applications as discussed above. Such MMICs are also well described in the literature; xe2x80x9cAn Indium Phosphide MMIC Amplifier For 180-205 GHzxe2x80x9d by Archer et al., IEEE Microwave and Wireless Components Letters, Volume 11, No. 1, January 2001, pp. 4-6; xe2x80x9cInP REMT Amplifier Development for G-Band (140-220 GHz) Applications by Lai et al., Digest Technical International Electron Devices Meeting, San Francisco, Calif. on Dec. 10-13, 2000, pp., 175-177; xe2x80x9cHigh Reliability Non-Hermetic,xe2x80x9d and xe2x80x9cExtremely High P1 dB MMIC Amplifiers for Ka-Band Applicationsxe2x80x9d by Lai et al., Gallium Arsenide Integrated Circuits (GAAsIC) System 2001, Twenty-Third Annual Technical Digest. Oct. 21-24, 2001, Baltimore, Md., pp. 115-117.
Such HEMTs are formed by conventional photolithography techniques and include a T-gate structure that is susceptible to damage during conventional metal lift-off techniques, thereby lowering the yield of such devices. More particularly with reference to FIG. 1, an intermediate process step for a HEMT is shown which illustrates the formation of the gate structures, identified with the reference numerals 20 and 22. These gate structures 20 and 22 are formed on top of a multi-layered structure, generally identified with the reference numeral 24. In order to form the desired gate structure, two levels of photo-resist 26 and 28 and masking steps are used to develop the T-gate structure 20 and 22 shown. An undesired metallization layer 30 is formed during the deposition of the metal on top of the photo-resist layers 26 and 28 to form the T-gate structures 20 and 22 shown.
The undesired metallization layer 30 and photoresist layers 26 and 28 are removed by conventional metal lift-off techniques which normally involve soaking the entire structure in a solvent solution, typically acetone. The solvent solution dissolves the photoresist layers 26 and 28 underneath the undesired gate metal layer 30. Once the photoresist layers 26 and 28 are dissolved, the undesired gate metal 30 is known to float off the wafer leaving the desired gate structures 20 and 22. Unfortunately, when the photoresist layers 26 and 28 are dissolved, the undesired gate metal layer 30 is known to break into pieces that can scratch or damage adjacent submicron structures, such as the T-gates 20 and 22 which at the neck are on the order of 0.1-0.15 microns. Damage to the gate structures 20 and 22 can result in a lower yield for the process. Thus, there is a need to prevent metal lift-off from damaging such gate structures to improve the yield.
The present invention relates to a process or improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.